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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD807 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 fiber optic receiver with quantizer and clock recovery and data retiming features meets ccitt g.958 requirements for stm-1 regeneratortype a meets bellcore tr-nwt-000253 requirements for oc-3 output jitter: 2.0 degrees rms 155 mbps clock recovery and data retiming accepts nrz data, no preamble required phase-locked loop type clock recovery no crystal required quantizer sensitivity: 2 mv level detect range: 2.0 mv to 30 mv single supply operation: +5 v or C5.2 v low power: 170 mw 10 kh ecl/pecl compatible output package: 16-lead narrow 150 mil soic reliance on external components such as a crystal or a saw filter, to aid frequency acquisition. the AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. the frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. at frequency lock, the frequency error is zero and the frequency detector has no further effect. the phase acquisition control loop then works to ensure that the output phase tracks the input phase. a patented phase detector has virtually eliminated pattern jitter throughout the AD807. the device vco uses a ring oscillator architecture and patented low noise design techniques. jitter is 2.0 degrees rms. this low jitter results from using a fully differential signal architecture, power supply rejection ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the ic. the device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. the user sets the jitter peaking and acquisition time of the pll by choosing a damping factor capacitor whose value determines loop damping. ccitt g.958 type a jitter transfer require- ments can easily be met with a damping factor of 5 or greater. device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. shorting the damping factor capacitor, c d , brings the clock output frequency to the vco center frequency. the AD807 consumes 170 mw and operates from a single power supply at either +5 v or ?.2 v. functional block diagram compensating zero loop filter signal level detector vco det + + f det retiming device phase-locked loop AD807 level detect comparator/ buffer quantizer pin nin thradj sdout clkoutp clkoutn dataoutp dataoutn cf1 cf2 product description the AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 mbps nrz data. the device, together with a pin diode/preamplifier combination, can be used for a highly integrated, low cost, low power sonet oc-3 or sdh stm-1 fiber optic receiver. the receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable thresh- old. the threshold is set with a single external resistor. the signal level detect circuit 3 db optical hysteresis prevents chatter at the signal level detect output. the pll has a factory-trimmed vco center frequency and a frequency acquisition control loop that combine to guarantee frequ ency acquisition without false lock. this elim inates a
rev. b C2C AD807?pecifications parameter condition min typ max unit quantizer?c characteristics input voltage range @ p in or n in 2.5 v cc v input sensitivity, v sense p in ? in , figure 1, ber = 1 10 ?0 2mv input overdrive, v od figure 1, ber = 1 10 ?0 0.001 2.5 v input offset voltage 50 500 v input current 510 a input rms noise ber = 1 10 ?0 50 v input peak-to-peak noise ber = 1 10 ?0 650 v quantizer?c characteristics upper ? db bandwidth 180 mhz input resistance 1m ? input capacitance 2pf pulsewidth distortion 100 ps level detect level detect range r thresh = infinite 0.8 2 4.0 mv r thresh = 49.9 k ? 4 5 7.4 mv r thresh = 3.4 k ? 14 20 25 mv response time dc-coupled 0.1 1.5 s hysteresis (electrical) r thresh = infinite 2.3 4.0 10.0 db r thresh = 49.9 k ? 3.0 5.0 9.0 db r thresh = 3.4 k ? 3.0 7.0 10.0 db sdout output logic high load = +4 ma 3.6 v sdout output logic low load = ?.2 ma 0.4 v phase-locked loop nominal center frequency 155.52 mhz capture range 155 156 mhz tracking range 155 156 mhz static phase error 2 7 ? prn sequence 4 20 degrees setup time (t su ) figure 2 3.0 3.2 3.5 ns hold time (t h ) figure 2 3.0 3.1 3.3 ns phase drift 240 bits, no transitions 40 degrees jitter 2 7 ? prn sequence 2.0 degrees rms 2 23 ? prn sequence 2.0 2.7 degrees rms jitter tolerance f = 10 hz 3000 unit intervals f = 6.5 khz 4.5 7.6 unit intervals f = 65 khz 0.45 1.0 unit intervals f = 1.3 mhz 0.45 0.67 unit intervals jitter transfer peaking (figure 11) c d = 0.15 f 0.08 db c d = 0.33 f 0.04 db bandwidth 65 92 130 khz acquisition time c d = 0.1 f2 23 ? prn sequence, t a = 25 c4 10 5 2 10 6 bit periods c d = 0.33 fv cc = 5 v, v ee = gnd 2 10 6 bit periods power supply voltage v min to v max 4.5 5.5 volts power supply current v cc = 5.0 v, v ee = gnd, t a = 25 c 25 34.5 39.5 ma pecl output voltage levels output logic high, v oh v cc = 5.0 v, v ee = gnd, t a = 25 c ?.2 ?.0 ?.7 volts output logic low, v ol referenced to v cc ?.0 ?.8 ?.7 volts symmetry (duty cycle) = 1/2, t a = 25 c, recovered clock output, pin 5 v cc = 5 v, v ee = gnd 50.1 54.1 % output rise / fall times rise time (t r ) 20%?0% 1.1 1.5 ns fall time (t f ) 80%?0% 1.1 1.5 ns specifications subject to change without notice. (t a = t min to t max , v cc = v min to v max , c d = 0.1 f, unless otherwise noted.)
rev. b AD807 C3C absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v input voltage (pin 12 or pin 13) . . . . . . . . . . . . . v cc + 0.6 v maximum junction temperature . . . . . . . . . . . . . . . . . 165 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c esd rating (human body model) . . . . . . . . . . . . . . . . . 500 v * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics: 16-lead narrow body soic package: ja = 110 c/w. 1 0 output noise offset overdrive sensitivity input (v) figure 1. input sensitivity, input overdrive setup t su hold t h dataoutp (pin 2) clkoutp (pin 5) figure 2. setup and hold time pin function descriptions pin no. mnemonic description 1 dataoutn differential retimed data output 2 dataoutp differential retimed data output 3v cc2 digital v cc for ecl outputs 4 clkoutn differential recovered clock output 5 clkoutp differential recovered clock output 6v cc1 digital v cc for internal logic 7 cf1 loop damping capacitor 8 cf2 loop damping capacitor 9av ee analog v ee 10 thradj level detect threshold adjust 11 av cc1 analog v cc for pll 12 nin quantizer differential input 13 pin quantizer differential input 14 av cc2 analog v cc for quantizer 15 sdout signal detect output 16 v ee digital v ee for internal logic pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dataoutn dataoutp v cc2 clkoutn clkoutp v cc1 cf1 cf2 v ee sdout av cc2 pin nin av cc1 thradj av ee AD807 ordering guide model temperature range package description package option AD807a-155br ?0 c to +85 c 16-lead narrowbody soic r-16a AD807a-155brrl7 ?0 c to +85 c 750 pieces, 7" reel r-16a AD807a-155brrl ?0 c to +85 c 2500 pieces, 13" reel r-16a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD807 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. b AD807 C4C definition of terms maximum, minimum and typical specifications specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. typical specifications are the mean of the distribution of the data for that parameter. if a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. this procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 stan dard deviations still provide a failure rate of only 3.4 parts per m illion. for all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. input sensitivity and input overdrive sensitivity and overdrive specifications for the quantizer involve offset voltage, gain and noise. the relationship between the logic output of the quantizer and the analog voltage input is shown in figure 1. for sufficiently large positive input voltage the output is always logic 1 and similarly, for negative inputs, the output is always logic 0. however, the transitions between output logic levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. w ithin this zone of confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. the width of this zone is determined by the input voltage noise of the quantizer (650 v at the 1 10 ?0 confidence level). the center of the zone of confusion is the quantizer input offset voltage ( 500 v maximum). input over- drive is the magnitude of signal required to guarantee correct logic level with 1 10 ?0 confidence level. with a single-ended pin-tia (figure 3), ac coupling is used and the inputs to the quantizer are dc biased at some common-mode potential. observing the quantizer input with an oscilloscope probe at the point indicated shows a binary signal with average value equal to the common-mode potential and instantaneous values both above and below the average value. it is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the quantizer sensitivity. referring to figure 1, since both positive and negative offsets need to be accommodated, the sensitivity is twice the overdrive. the AD807 quantizer has 2 mv sensitivity. with a differential tia (figure 3), sensitivity seems to improve from observing the quantizer input with an oscilloscope probe. this is an illusion caused by the use of a single-ended probe. a 1 mv peak-to-peak signal appears to drive the AD807 quantizer. however, the single-ended probe measures only half the signal. the true quantizer input signal is twice this value since the other quantizer input is a complementary signal to the sig- nal being observed. response time response time is the delay between removal of the input signal and indication of loss of signal (los) at sdout. the response time of the AD807 (1.5 s maximum) is much faster than the sonet/sdh requirement (3 s response time 100 s). in practice, the time constant of the ac coupling at the quantizer input determines the los response time. nominal center frequency this is the frequency at which the vco will oscillate with the loop damping capacitor, c d , shorted. tracking range this is the range of input data rates over which the AD807 will remain in lock. capture range this is the range of input data rates over which the AD807 will acquire lock. static phase error this is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. gate delays between the signals that define static phase error, and ic input and output signals prohibit direct measurement of static phase error. data transition density, this is a measure of the number of data transitions, from ??to ??and from ??to ?,?over many clock periods. is the ratio (0 1) of data transitions to bit periods. jitter this is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or unit intervals (ui). jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. jitter on the recovered clock causes jitter on the retimed data. output jitter this is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence (prn sequence). jitter tolerance jitter tolerance is a measure of the AD807? ability to track a jittery input data signal. jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. the pll must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. in order for the vco output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. the modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. hence, the pll can never perfectly track jittered data. however, the magnitude of the phase error depends on the gain around the loop. at low fre- quencies, the integrator of the AD807 pll provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. at frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. the AD807 output will have a bit error rate less than 1 10 ?0 when in lock and retiming input data that has the ccitt g.958 specified jitter applied to it. jitter transfer (refer to figure 11) the AD807 exhibits a low-pass filter response to jitter applied to its input data.
rev. b AD807 C5C bandwidth this describes the frequency at which the AD807 attenuates sinusoidal input jitter by 3 db. peaking this describes the maximum jitter gain of the AD807 in db. damping factor, damping factor, desc ribes the compensation of the second order pll. a larger value of corresponds to more damping and less peaking in the jitter transfer function. acquisition time this is the transient time, measured in bit periods, required for the AD807 to lock onto input data from its free-running state. symmetry?ecovered clock duty cycle symmetry is calculated as (100 on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its ??level and its ??level. bit error rate vs. signal-to-noise ratio AD807 bit error rate vs. signal-to-noise ratio performance is shown in tpc 6. wideband amplitude noise is summed with the input data signal as shown in figure 4. performance is shown for input data levels of 5 mv and 10 mv. v cm 2mv p-p scope probe AD807 quantizer epitaxx erm504 v cm binary output a. single-ended input application v cm 1mv p-p scope probe AD807 quantizer ad8015 differential output tia v cm binary output +out out b. differential input application figure 3. (aCb) single-ended and differential input applications + + 50 50 0.47 f 0.47 f 75 1.0 f 100 gnd 5v + power combiner power combiner pin nin differential signal source power splitter noise source filter 100mhz d.u.t. AD807 &
+

(- -! * 0 1
v be 0.8v av cc2 differential input current sources headroom 0.7v 0.5ma 1ma 0.5ma av ee 400 400 a. quantizer differential input stage 5.9k 1.2v +v be av ee thradj 94.6k *
4 150 v ee sdout 150 v cc1 i oh i ol ( ) .()5*/ 450 450 v cc2 differential input 2.5ma v ee d. pll differential output stagedataout(n), clkout(n) figure 5. (aCd) simplified schematics
rev. b AD807 C6C typical performance characteristics signal detect level mv 200.0e+3 0.0e+0 0.0 30.0 5.0 r thresh 10.0 15.0 20.0 25.0 160.0e+3 140.0e+3 100.0e+3 80.0e+3 120.0e+3 180.0e+3 60.0e+3 40.0e+3 20.0e+3 35.0 tpc 1. signal detect level vs. r thresh temperature c 35.0e 3 0.0e+0 40 80 20 signal detect level volts 0204060 25.0e 3 15.0e 3 20.0e 3 30.0e 3 10.0e 3 5.0e 3 100 r thresh = open r thresh = 49.9k r thresh = 0 tpc 2. signal detect level vs. temperature temperature c 9.00 3.00 40 80 20 electrical hysteresis db 0204060 7.00 5.00 6.00 8.00 4.00 100 r thresh = open r thresh = 49.9k r thresh = 0 tpc 3. signal detect hysteresis vs. temperature supply voltage volts 35.000e 3 0.000e+0 4.4 5.6 4.6 signal detect level volts 4.8 5.0 5.2 5.4 25.000e 3 20.000e 3 10.000e 3 5.000e 3 15.000e 3 30.000e 3 r thresh = open r thresh = 49.9k r thresh = 0 tpc 4. signal detect level vs. supply voltage power supply v 8.00 0.00 4.4 5.6 4.6 electrical hysteresis db 4.8 5.0 5.2 5.4 6.00 5.00 2.00 1.00 4.00 7.00 3.00 r thresh = open r thresh = 49.9k r thresh = 0 tpc 5. signal detect hysteresis vs. power supply 1 2 1 2 2 s n ) ( erfc 10 12 14 16 18 20 22 24 s/n db 1e 1 5e 2 3e 2 2e 2 1e 2 1e 3 1e 4 1e 5 1e 6 1e 8 1e 10 1e 12 bit error rate 1278 nsn 1276 1279 1277 tpc 6. bit error rate vs. signal-to-noise ratio
rev. b AD807 C7C rms jitter degrees 30 0 1.4 2.3 1.5 percentage % 1.6 1.7 1.8 2.2 20 5 15 25 10 1.9 2.0 2.1 test conditions worst-case: 40 c, 4.5v tpc 7. output jitter histogram frequency hz 1e+3 100e 3 10e+0 10e+6 jitter tolerance ui 10e+0 100e+0 1e+3 10e+3 100e+3 100e+0 1e+0 1e+6 AD807 sonet mask tpc 8. jitter tolerance noise v p-p @ 311mhz 3.0 0 0 0.6 0.1 jitter ns p-p 0.2 0.3 0.4 0.5 2.0 1.0 1.0 0.7 0.8 0.9 psr no filter cmr psr with filter tpc 9. output jitter vs. supply noise and output jitter vs. common mode noise theory of operation quantizer the quantizer (comparator) has three gain stages, providing a net gain of 350. the quantizer takes full advantage of the extra fast complementary bipolar (xfcb) process. the input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with common- mode voltage as high as the positive supply. the input offset volt age is factory trimmed and guaranteed to be less than 500 v. xfcb? dielectric isolation allows the different blocks within this m ixed-signal ic to be isolated from each other, hence the 2 mv sensitivity is achieved. traditionally, high speed compara- tors are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mv. the AD807 quantizer toggles at 650 v (1.3 mv sensitivity) at the input without making bit errors. when the input signal is lowered below 650 v, circuit performance is dominated by input noise, and not crosstalk. 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f ferrite bead optional filter 0.1 f 50 309 50 50 3.65k +5v 10 f choke bias tee 311mhz noise input 0.1 f 0.1 f 500 500 13 12 14 11 6 3 pin nin av cc2 av cc1 v cc1 v cc2 AD807 0.1 f quantizer input figure 6. power supply noise sensitivity test circuit 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 50 309 50 50 3.65k +5v 10 f choke bias tee 311mhz noise input 0.1 f 0.1 f 500 500 13 12 14 11 6 3 pin nin av cc2 av cc1 v cc1 v cc2 AD807 0.1 f quantizer input figure 7. common-mode rejection test circuit signal detect the input to the signal detect circuit is taken from the first stage of the quantizer. the input signal is first processed through a gain stage. the output from the gain stage is fed to both a positive and a negative peak detector. the threshold value is subtracted from the positive peak signal and added to the negative peak signal. the positive and negative peak signals are then compared. if the positive peak, pos, is more positive than the negative peak, neg, the signal amplitude is greater than the threshold, and the output, sdout, will indicate the presence of signal by remain- ing low. when pos becomes more negative than neg, the signal amplitude has fallen below the threshold, and sdout will indicate a loss of signal (los) by going high. the circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. this means that the input data amplitude needs to reach twice the set los threshold before sdout will signal that the data is again valid. this corresponds to a 3 db optical hysteresis.
rev. b AD807 C8C AD807 comparator stages and clock recovery pll pin nin threshold bias + + ihys ithr sdout positive peak detector negative peak detector level- shift up level- shift down figure 8. signal level detect circuit block diagram phase-locked loop the phase-locked loop recovers clock and retimes data from nrz data. the architecture uses a frequency detector to aid initial frequency acquisition; refer to figure 9 for a block diagram. note the frequency detector is always in the circuit. when the pll is locked, the frequency error is zero and the frequency detector has no further effect. since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition. det f det data input s + 1 retiming device 1 s vco recovered clock output retimed data output figure 9. pll block diagram the frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the vco. during the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the vco. these pulses occur on the cycle slips between the data frequency and the vco frequency. with a maximum density data pattern (1010 . . . ), every cycle slip will produce a pulse at the frequency detector output. however, with random data, not every cycle slip produces a pulse. the density of pulses at the frequency detector output increases with the density of data transitions. the probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. after the frequency error has been reduced to zero, the frequency detector output will have no further pulses. at this point the pll begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). briefly, the measurement of zero phase error does not cause the vco phase to increase to above the average run rate set by the data frequency. the jitter created by a 2 7 ? pseu dorandom code is 1/2 degree, and this is small compared to random jitter. the jitter bandwidth for the pll is 0.06% of the center fre- quency. this figure is chosen so that sinuso idal input jitter at 92 khz will be attenuated by 3 db. the damping ratio of the pll is user programmable with a single external capacitor. at 155 mhz, a damping ratio of 5 is obtained with a 0.15 f capacitor. more generally, the damp- ing ratio scales as (f data c d ) 1/2 . a lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. however, at damping ratios approaching one, the acquisi- tion time no longer scales directly with capacitor value. the acquisition time has two components: frequency acquisition and phase acquisition. the frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop band- width of the pll and is independent of the damping ratio. thus, the 0.06% fractional loop bandwidth sets a minimum acquisition time of 2000 bit periods. note the acquisition time for a damping factor of one is 15,000 bit periods. this comprises 13,000 bit periods for frequency acquisition and 2,000 bit peri- ods for phase acquisition. compare this to the 400,000 bit periods acquisition time specified for a damping ratio of 5; this consists entirely of frequency acquisition, and the 2,000 bit periods of phase acquisition is negligible. while a lower damping ratio affords faster acquisition, it also allows m ore peaking in the jitter transfer response (jitter peaking). for example, with a damping ratio of 10, the jitter peaking is 0.02 db, but with a damping ratio of 1, the peaking is 2 db. center frequency clamp (figure 10) an n-channel fet circuit can be used to bring the AD807 vco center frequency to within 10% of 155 mhz when sdout indicates a loss of signal (los). this effectively reduces the frequency acquisition time by reducing the frequency error between the vco frequency and the input data frequency at clamp release. the n-fet can have ?n?resistance as high as 1 k ? and still attain effective clamping. however, the chosen n-fet should have greater than 10 m ? ?ff?resistance and less than 100 na leakage current (source and drain) so as not to alter normal pll performance. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 AD807 dataoutn dataoutp v cc2 clkoutn clkoutp v cc1 cf1 cf2 v ee sdout av cc2 pin nin av cc1 thradj av ee n_fet c d figure 10. center frequency clamp schematic frequency hz 10 20k 0.02db/div 100 1k 10k c d peak 0.1 0.15 0.22 0.33 0.12 0.08 0.06 0.04 figure 11. jitter transfer vs. c d
rev. b AD807 C9C AD807 dataoutn dataoutp v cc2 clkoutn cf1 cf2 v ee sdout pin nin av cc1 thradj av ee 50 strip line equal length c7 c10 are 0.1 f bypass capacitors right angle sma connector outer shell to gnd plane all resistors are 1% 1/8 watt surface mount tpx o test points are vectorboard k24a/m pins notes: tp7 tp8 j5 sdout c9 r13 301 r14 49.9 r15 49.9 c13 0.1 f c14 0.1 f r16 3.65k c12 0.1 f j6 j7 pin nin vector pins spaced for rn55c type resistor; component shown for reference only v cc1 clkoutp av cc2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 note: interconnection run under dut c10 r thresh tp5 tp6 tp1 tp2 cd vector pins spaced through-hole capacitor on vector cups; component shown for reference only r5 100 r6 100 50 strip line equal length r10 154 r9 154 c7 r7 100 r8 100 c8 r12 154 r11 154 c11 10 f tp3 tp4 5v gnd r2 100 r1 100 c3 0.1 f c4 0.1 f c5 0.1 f c6 0.1 f r4 100 r3 100 c2 0.1 f dataoutn dataoutp clkoutn clkoutp c1 0.1 f j1 j2 j3 j4 figure 12. evaluation board schematic figure 13. evaluation board pictorials circuit side 08-002901-02 rev a silkscreen top 08-002901-03 rev a int2 08-002901-08 rev a component side 08-002901-01 rev a int1 08-002901-07 rev a soldermask top 08-002901-04 rev a
rev. b AD807 C10C AD807 dataoutn dataoutp v cc2 clkoutn cf1 cf2 v ee sdout pin nin av cc1 thradj av ee sdout tp7 r14 50 r15 50 v cc1 clkoutp av cc2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 tp5 tp1 tp2 cd r5 100 r6 100 r10 154 r9 154 c7 r7 100 r8 100 c8 r12 154 r11 154 tp4 r2 100 r1 100 c2 0.1 f c3 0.1 f c4 0.1 f c5 0.1 f r4 100 r3 100 c2 0.1 f dataoutn dataoutp clkoutn clkoutp notes: 1. all capacitors are chip, 15pf are mica. 2. 150nh are smt 3. c7, c8, c10, c11 are 0.1 f bypass capacitors c1 0.1 f j1 j2 j3 j4 tp6 r13 thradj c10 c11 c15 0.1 f c14 0.1 f r16 301 c12 2.2 f r17 3.65k c13 0.1 f nc i in nc v byp +v s +out v s out ad8015 1 2 3 4 8 7 6 5 abb hafo 1a227 fc housing 0.8a/w, 0.7pf 2.5ghz 0.01 f 0.1 f nc = no connect 0.1 f 10 f 15pf 150nh 150nh 15pf tp3 5v c9 10 f 50 line 50 line figure 14. low cost 155 mbps fiber optic receiver schematic table i. AD807?d8015 fiber optic receiver circuit: output bit error rate and output jitter vs. input power average optical input power output bit output jitter (dbm) error rate (ps rms) ?.4 loses lock ?.5 7.5 10 ? ?.6 9.4 10 ? ?.7 0 10 ?4 ?.0 to ?5.5 0 10 ?4 <40 ?6.0 3 10 ?2 <40 ?6.5 4.8 10 ?0 ?7.0 2.8 10 ? ?8.0 1.3 10 ? ?9.0 1.0 10 ? ?9.2 1.9 10 ? ?9.3 loses lock applications low cost 155 mbps fiber optic receiver the AD807 and ad8015 can be used together for a complete 155 mbps fiber optic receiver (quantizer and clock recovery, and transimpedance amplifier) as shown in figure 14. the pin diode front end is connected to a single mode 1 300 nm laser source. the pin diode has 3.3 v reverse bias, 0.8 a/w responsively, 0.7 pf capacitance, and 2.5 ghz bandwidth. the ad8015 outputs (p out and n out ) drive a differential, const ant impedance (50 ? ) low-pass filter with a 3 db cutoff of 100 mhz. the outputs of the low-pass filter are ac coupled to the AD807 inputs (pin and nin). the AD807 pll damp- ing factor is set at 7 using a 0.22 f capacitor. 503mv 100mv/ div 497mv 48.12ns 1ns/div 58.12ns figure 15. receiver output (data) eye diagram, C7.0 dbm optical input 503mv 100mv/ div 497mv 49.12ns 1ns/div 59.12ns figure 16. receiver output (data) eye diagram, C36.0 dbm optical input
rev. b AD807 C11C AD807 dataoutn dataoutp v cc2 clkoutn cf1 cf2 v ee sdout pin nin av cc1 thradj av ee sdout v cc1 clkoutp av cc2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 cd r5 100 r6 100 r10 154 r9 154 c7 0.1 f r7 100 r8 100 c8 0.1 f r12 150 r11 150 r2 100 r1 100 c2 0.1 f c3 0.1 f c4 0.1 f c5 0.1 f r4 100 r3 100 c6 0.1 f c1 0.1 f j1 j2 j3 j4 r13 thradj c11 0.1 f c10 0.1 f r14 47 r15 47 r16 330 c9 10 f 5v c13 0.1 f c14 0.1 f 30pf 30pf noise filter 120nh r17 3.9k c12 0.1 f epitaxx erm504 1 2 pin tia 1 f note: pin tia pin 4 (case) is connected to ground figure 17. AD807 application with epitaxx pintransimpedance amplifier module the entire circuit was enclosed in a shielded box. table i sum- marizes results of tests performed using a 2 23 -1 prn sequence, and varying the average power at the pin diode. the circuit acquires and maintains lock with an average input power as low as ?9.25 dbm. table ii. AD807?pitaxx erm504 pin tia 155 mbps fiber optic receiver circuit: output bit error rate and output jitter vs. average input power average optical input power output bit output jitter (dbm) error rate (ps rms) 0 0.0 10 ?0 29 ? 0.0 10 ?0 35 ?0 0.0 10 ?0 40 ?0 0.0 10 ?0 37 ?0 0.0 10 ?0 33 ?2 0.0 10 ?0 35 ?4 0.0 10 ?0 36 ?5 0.0 10 ?0 39 ?5.5 0.0 10 ?0 40 ?6 0.0 10 ?0 41 ?7.0 0.0 10 ?0 42 ?7.6 0.5 10 ?0 43 ?8.0 4 10 ? 50 sonet (oc-3)/sdh (stm-1) fiber optic receiver circuit a light wave receiver circuit for sonet/sdh application at 155 mbps is shown in figure 17, with test results given in table ii. the circuit operates from a single 5 v supply, and uses two major components: an epitaxx erm504 pin-tia module with agc, and the AD807 ic. a 120 mhz, third order, low-pass butterworth filter at the output of the pin-tia module provides adequate bandwidth (70% of the bit rate), and attenuates high frequency (out of band) noise. 250mv 50mv/ div 250mv 38.12ns 1ns/div 48.12ns figure 18. receiver output (data) eye diagram, 0 dbm optical input 250mv 50mv/ div 250mv 38.12ns 1ns/div 48.12ns figure 19. receiver output (data) eye diagram, C38 dbm optical input
rev. b C12C c00862C0C12/00 (rev. b) printed in u.s.a. AD807 using the AD807 ground planes use of one ground plane for connections to both analog and digital grounds is recommended. power supply connections use of a 10 f capacitor between v cc and ground is recom- mended. care should be taken to isolate the 5 v power trace to v cc2 (pin 3). the v cc2 pin is used inside the device to provide the clkout and dataout signals. use of 0.1 f capacitors between ic power supply and ground is recommended. power supply decoupling should take place as close to the ic as possible. refer to the schematic, figure 12, for recommended connections. transmission lines use of 50 ? transmission lines are recommended for pin, nin, clkout, and dataout signals. terminations termination resistors should be used for pin, nin, clkout, and dataout signals. metal, thick film, 1% tolerance resistors are recommended. termination resistors for the pin, nin sig nals should be placed as close as possible to the pin, nin pins. connections from 5 v to load resistors for pin, nin, clkout, and dataout signals should be individual, not daisy chained. this will avoid crosstalk on these signals. loop damping capacitor, c d a ceramic capacitor may be used for the loop damping capaci- tor. using a 0.15 f, +20% capacitor for a damping factor of five provides < 0.1 db jitter peaking. AD807 output squelch circuit a simple p-channel fet circuit can be used in series with the output signal ecl supply (v cc2 , pin 3) to squelch clock and data outputs when sdout indicates a loss of signal (figure 20). the v cc2 supply pin draws roughly 61 ma (14 ma for each of 4 ecl loads, plus 5 ma for all 4 ecl output stages). this means that selection of a fet with on resis tance of 0.5 ? will affect the common mode of the ecl outputs by only 31 mv. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 AD807 dataoutn dataoutp v cc2 clkoutn clkoutp v cc1 cf1 cf2 v ee sdout av cc2 pin nin av cc1 thradj av ee p_fet 5v bypass cap to v cc1 , av cc , av cc2 figure 20. squelch circuit schematic outline dimensions dimensions shown in inches and (mm). 16-lead small outline ic package (r-16a) 16 9 8 1 0.1574 (4.00) 0.1497 (3.80) 0.3937 (10.00) 0.3859 (9.80) 0.050 (1.27) bsc pin 1 0.2440 (6.20) 0.2284 (5.80) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19)

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